1. Field of the Invention
The present invention relates to a doping method in a junction formation process, in particular, a shallow junction formation process, of a semiconductor device, and a semiconductor device using the same.
2. Description of the Related Art
For metal oxide semiconductor field effect transistors (MOSFET), high performance has been achieved by microfabrication in view of processing size. However, due to the shortened channel length, phenomena called short channel effect and hot carrier phenomena have arisen and prevented improvement of the performance of the device.
To avoid such negative impact, it is necessary to make the source/drain junction shallow. In addition, to increase the current drivability of transistors, the resistance (layer resistance) of the doping layer of the source and the drain needs to be as low as possible. International Technology Roadmap for Semiconductors (ITRS 2002 Update) requires realization of a source/drain junction depth of 10 nm and a sheet resistance of 360 Ω by the year 2007.
Conventionally, as a technique for forming a shallow source/drain junction, a combination of low speed ion implantation and rapid thermal annealing process (A. Ono et al.: 2000 Symposium on VLSI Technology Digest of Technical Papers, p. 14), plasma doping (Bunji Mizuno, Oyo Buturi, Vol.70, No.12, p. 1458–1462, 2001), elevated source/drain due to selective epitaxial growth (Denshi Zairyo (Electronic Materials and Parts), November sppl. and Vol./2002, Guide Book of VLSI Production and Testing Equipment, p. 95–99, 2001), solid phase diffusion (Japanese Patent Application Laid-Open No. 8-167658) and laser doping (K. Shibahara et al.: 2001 Solid State Devices and Materials, p. 236).